TYPE states IS (state1,state2 ... state8);
SIGNAL current_state, next_state : states;
BEGIN
current_state_update: process(clk, reset)
begin
if reset='1' then
current_state<=state1;
elsif (clk'event and clk='1') then
current_state<=next_state;
end if;
end process current_state_update;
next_state_up : process(current_state)
begin
case current_state is
when state1=> next_state<=state2;
when state2=> next_state<=state3;
....
when state8=> next_state<=state1;
end case;
end process next_state_up;
output_gen: process(current_state)
begin
case current_state is
when state1=> output<="000";
when state2=> output<="001";
....
when state8=> output<="111";
when others=> output<="000";
end case;
end process output_gen;