FSM design questions...

fsm design

Hi all,

If anyone of you solved the following FSM design problems then please post the answers/suggestions/designs :

1. Design a state-machine to give an output ’1’ when the number of A’s are even and number of B’s are odd. The input is in the form of a serial-stream (one-bit per clock cycle). The input s could be of t he type A, B or C. At any given clock cycle, the output is a ’1’, provided the number of A’s are even and number of B’s are odd. At any given clock cycle, the out put is a ’0’, if the above condition is not satisfied.

2. Design a FSM to detect the sequence ‘abca’ when the inputs can be ‘abcd’.

3. Design a finite state machine for a modulo-3 counter when x=0, and modulo-4 counter when x=1.

4. Design a logic which mimics a infinite width register. It takes input serially 1 bit at a time. Output is asserted high when this register holds a value which is divisible by 5.

thanks,
sp3

fsm design questions

Hi,

For each of the problem,

1. find out input and output of the FSM
2. draw a state diagram based on specifications
3. find out combo block, next state block and seq block
4. develop the code

It is better if you give it a try on your own so that you can learn more.

Thanks.