Is it possible to create a frequency multiplier with verilog that can be implemented in a FPGA? That means given a input signal of frequency f can a circuit be made that calculates the frequency M*f ???
Actually I wanted to know how can i create another signal which has a frequency M times the input signal frequency where M>1. So that the signal generated has a frequency greater than that of the input frequency. ADPLL helps me get a signal which has a frequency lower than that of the input signal.
What if my system has only one input and I need to generate a clock using that signal. Like I need to generate the clock for the K counter and ID counter (DCO) which are multiples of the clock signal given as input.
Making use of DLLs may help for your problem. Have the same signal passed through Delay loops to achieve a higher frequency for the input. I have not synthesized one, but have seen the concept of this in Xilinx.