Frequency mismatch of burst cdr based on gated VCO

[marcel]

gated vco

Hi guys,
I have encountered a issue during designing burst cdr based on gated VCO for GPON.There is a big mismatch between the VCO frequency of reference PLL and the gated VCOs. But the GPON requires the frequency mismatch between the received data and the sampling clock is less than 1/(2*72) .How can I decrease the frequency mismatch to meet the GPON requirement? Could anybody give me any advice? Whether do I need to add a frequency detector between the reference PLL's VCO and gated VCO to correct the frequency of the gated VCO or not? If so, how can I implement the frequency detector and correcting circuit?

Thanks in advance

 

[longyawn]

Are the VCO belonged to the reference PLL the same as gated VCO?

 

[marcel]

Yes! Could you give some comments?