manikandanmadurai
Newbie level 2
Hi,
i have to design a "programmable frequency divider" for pll(to be used as bfsk). the VCO output is 400 and 420 MHz. reference input is 10MHz.the divider N values are then 40 and 42..
1. pls help me with some links that would be useful for my prestudy
2.which architecture is recommended
3. what does "programmable" actually means
4. i shud start with behavior modelling(verilog-a)..need some references
CMOS 0.35u process
i have to design a "programmable frequency divider" for pll(to be used as bfsk). the VCO output is 400 and 420 MHz. reference input is 10MHz.the divider N values are then 40 and 42..
1. pls help me with some links that would be useful for my prestudy
2.which architecture is recommended
3. what does "programmable" actually means
4. i shud start with behavior modelling(verilog-a)..need some references
CMOS 0.35u process