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From my experience, which is very very little, compared to others, I know that there is Xilinx (web pack which can be downloaded and installed , it free or trial for study purpose) but I think this one is for FPGA synthesis, but it can do RTL synthesis too. Another tool that you can use is Icarus Verilog (iverilog) which you can call it the command line with "-S " flag which will produce an EDIF format file (which is the netlist from the synthesis), read the manual of Icarus Verilog.
But I strongly recommend for you to use Xilinx , which can synthesize from Verilog and from VHDL ito standard gate-level (INV, AOI, DFF etc. ). there is no optimization or time constraints that you can use in this program(I hope I'm wrong). I'm also interested in such tools(free), so please let me know if you could find a better solution( maybe you can find somewhere, in an University some tools that you can work with like synopsys Design Compiler or cadence RTL Compiler or BuildGates, and if you can you can upload the source there, and synthesis, but only for educational purpose ).
For Xilinx you don't need an fpga board necessary, you can synthesize from source code (Verilog or VHDL), an dit will generate a generic(standard) schematic(this one it won't have FPGA characteristics like LUTs, it will be general, and you can use it in your asic project, as long as you don't need optimization).
I hope this will help you, please post if you find something else, because as I said I'm interested too.
And I forgot to mention that in Xilinx(as I remember) you can't load a standard cell library....
You're right, I made a mistake, I'm still a student, and in my University students if they want they can use some of the software shipped with the "University Software Program" or something like that(Cadenc* & Synops*, provide some tools), for study purpose.
I don't know if adilkhan123 is still a student, if he needs to synthesize something, I'm thinking he's hired in a company with software access , but he is asking for free tool, so I thought he's still a student(a lot of students are reading this forum), but once again, I made a mistake assuming that, probably adilkhan wants to learn it in private(at home), but last thing I can imagine is that he's synthesizing by his own, to make a chip to sell, and not for study.
And I didn't said that the University "do ASIC synthesis for free", I said that he will have access(if he's a student) to some software tools(old versions) but still good. Nobody will synthesize for him, he will need to do it by his own, start learning, that's what I meant, and once again sorry for miss-interpretation .