Ace-X
Advanced Member level 2

Was posted at OpenCores discussion list.
h**p://www.infotech.tu-chemnitz.de/~knoll/vhdl_pci_bridge/
Some details:
----------------
Characteristics of the PCI bus interface unit within the FPGA:
- supports PCI-Master and PCI-Slave operation
- 33 MHz / 32Bit – PCI bus support
- complies with PCI-Spezification 2.1 (not officially tested/approved/certified !)
- 5ndependent clock for PCI <- -> Local Bus by means of transmit and receive FIFO buffer
- configurable FIFO buffer size
Additional Features:
- I²C-Bus-Interface
- programmable clock controller for local bus clock
- variable / freely defniable local bus structure and protocol (adaption to various Microcontrollers and full custom chips possible)
The VHDL has been carefully drimmed not to use Xilinx specific components. Hence, it might be possible to transfer the PCI core to ALTERA FPGAs as well.
h**p://www.infotech.tu-chemnitz.de/~knoll/vhdl_pci_bridge/
Some details:
----------------
Characteristics of the PCI bus interface unit within the FPGA:
- supports PCI-Master and PCI-Slave operation
- 33 MHz / 32Bit – PCI bus support
- complies with PCI-Spezification 2.1 (not officially tested/approved/certified !)
- 5ndependent clock for PCI <- -> Local Bus by means of transmit and receive FIFO buffer
- configurable FIFO buffer size
Additional Features:
- I²C-Bus-Interface
- programmable clock controller for local bus clock
- variable / freely defniable local bus structure and protocol (adaption to various Microcontrollers and full custom chips possible)
The VHDL has been carefully drimmed not to use Xilinx specific components. Hence, it might be possible to transfer the PCI core to ALTERA FPGAs as well.