cirand
Junior Member level 3
meninger perrot
Does anyone has the experience on fractional N PLL design?
it seems very difficult to implement it in a chip for me. many papers
have describled the FN-PLL principle, but few of them refer to the detailed realization methods.Can anybody give me any advice ? such as what is the design flow, which tool should be to use, and any good articles on this field? thanks.
Does anyone has the experience on fractional N PLL design?
it seems very difficult to implement it in a chip for me. many papers
have describled the FN-PLL principle, but few of them refer to the detailed realization methods.Can anybody give me any advice ? such as what is the design flow, which tool should be to use, and any good articles on this field? thanks.