frac-N prescalars

[venn_ng]

I have a dumb question on frac-N dividers. Why do we use asynchronous dividers (like pre-scalars 2/3 or multi-modulus dividers for example) instead of synchronous dividers in frac-N PLLs? We have to meet the timing for the first frac-N divider at Tout (Tout is the time period of PLL output) and it seems to me it's same in both the cases. Also, async dividers accumulate jitter. Then what's the advantage of prescalar over synchronous counters for example?

 

[dick_freebird]

A lot of the time the PLL product is aimed at the highest
achievable Fin, and that is achievable only with very
simple circuitry - like a dynamic flip flop, pulse swallowing
prescaler, which can run octaves faster than a fed-back
toggle DFF of traditional CMOS logic style.

The prescaler takes care of the frequency challenge
relieving the pressure on the larger counter-chains.