FPGA Verilog problems

[yfeng]

hi,everyone,
I want to design a frequence divider, the dividing ratio is 2000; It has a clk input and three same clock outputes, when i use modelsim-Altera simulation,problems come, there are only one clock output,others are zeros;however,when i use three always structure ,the output is all ok;I don't know why?

Following is my verilog codes:
This is my previous codes:
module ft(
inclk1,
clkout3,
clkout4,
clkout5
);

input wire inclk1;
output clkout3;
output clkout4;
output clkout5;


parameter N=2000;
parameter bitlongth=15;
reg clkout3=0;
reg clkout4=0;
reg clkout5=0;
reg[bitlongth:0] counter=16'b0;

always @(inclk1)
begin
if(counter==(2*N-1))
begin
counter<=0;
end
else
counter<=counter+1;
end
always @(counter)
begin
if(counter<=1)
begin
clkout3<=0;
clkout4<=0;
clkout5<=0;
end
else if(counter==2) begin
clkout3<=1;
clkout4<=1;
clkout5<=1;
end else
clkout3<=0;
clkout4<=0;
clkout5<=0;
end
endmodule


This is later codes,which has three "always" structures:
module ft(
inclk1,
clkout3,
clkout4,
clkout5
);

input wire inclk1;
output clkout3;
output clkout4;
output clkout5;


parameter N=2000;
parameter bitlongth=15;
reg clkout3=0;
reg clkout4=0;
reg clkout5=0;
reg[bitlongth:0] counter=16'b0;

always @(inclk1)
begin
if(counter==(2*N-1))
begin
counter<=0;
end
else
counter<=counter+1;
end
always @(counter)
begin
if(counter<=1)
begin
clkout3<=0;
// clkout4<=0;
// clkout5<=0;
end
else if(counter==2) begin
clkout3<=1;
// clkout4<=1;
// clkout5<=1;
end else
clkout3<=0;
// clkout4<=0;
// clkout5<=0;
end
always @(counter)
begin
if(counter<=1)
begin
// clkout3<=0;
clkout4<=0;
// clkout5<=0;
end
else if(counter==2) begin
// clkout3<=1;
clkout4<=1;
// clkout5<=1;
end else
// clkout3<=0;
clkout4<=0;
// clkout5<=0;
end
always @(counter)
begin
if(counter<=1)
begin
//clkout3<=0;
//clkout4<=0;
clkout5<=0;
end
else if(counter==2) begin
// clkout3<=1;
// clkout4<=1;
clkout5<=1;
end else
// clkout3<=0;
// clkout4<=0;
clkout5<=0;
end
endmodule
TestBench:
`timescale 1 ns/ 1 ns
module ft_vlg_tst();
reg inclk1;
// wires
wire clkout3;
wire clkout4;
wire clkout5;

// assign statements (if any)
ft i1 (
// port map - connection between master ports and signals/registers
.clkout3(clkout3),
.clkout4(clkout4),
.clkout5(clkout5),
.inclk1(inclk1)
);
initial
begin
inclk1=0;
end

always #250 inclk1=~inclk1;

always
begin
#3500000 $stop;
end
endmodule

 

[j_andr]

if(counter==(2*N-1))

are you sure you mean this ?

only one clock output,others are zeros

this is a piece of your code, compare else if and else part

    else if(counter==2) 
         begin
           clkout3<=1; 
           clkout4<=1;
           clkout5<=1; 
         end 
    else
       clkout3<=0;
       clkout4<=0;
       clkout5<=0; 
 end

J.A

 

[yfeng]

yeah, i hope to get the same width pulse as the clock input in the output,such as these picture
From these pictures, you can see different codes' simulation. Apparently, using three "always" structures clkout3 ,clkout4 and clkout5 have outputes, but one structure only clkout3 outputes. What's wrong in my codes?

 

[Nithin_eda]

you have missed begin/end in else block
else if(counter==2)
begin
clkout3<=1;
clkout4<=1;
clkout5<=1;
end
else
begin // This is not there
clkout3<=0;
clkout4<=0;
clkout5<=0;
end // This is not there

This should work

 

[yfeng]

oh,yeah, it works well,thanks.
I still puzzle on the question:
In the else block,if no begin/end,why clkout3 still ouput clock?
if the expression in else block clkout3<=0; works,
should the next two expressiones be valid?
such as clkout4<=0;
clkout5<=0;

 

[FvM]

What's wrong in my codes?

I think, you should better read the answers to your posts. Isn't it enough to mark the error finding in bold letters? Should it be written in red?

P.S.:

should the next two expressiones be valid?
such as clkout4<=0;
clkout5<=0;

They are "valid" indeed. Executed unconditionally and holding clkout4 and clkout5 low.

 

[yfeng]

thanks to your caution,but I mean ,since "clkout3<=1" executes after counter==2,why "clkout4<=1","clkout5<=1" don't.

 

[j_andr]

thanks to your caution,but I mean ,since "clkout3<=1"
executes after counter==2,why "clkout4<=1","clkout5<=1" don't.

I think, you should better read the answers to your posts.

    if(counter<=1) 
      begin
         clkout3<=0;
         clkout4<=0;
         clkout5<=0; 
      end 
    else 
    if(counter==2) 
     begin
       clkout3<=1; 
       clkout4<=1;
       clkout5<=1; 
    end 
    else
      clkout3<=0;

clkout4<=0;
clkout5<=0;

assignments to clkout4/5 are outside if/else if and as the last assignments they 'cover' the previous;
J.A

 

[yfeng]

oh, yes,you are right, I comprehend it now.
I consider the "else" block including the following three expressions.
I am wrong.
Thanks guys.