alexan_e
Administrator
I'm using a 10ns sram IS61LV51216 (https://www.eng.auburn.edu/~nelson/courses/elec5260_6260/61LV51216 SRAM.pdf) with a Cyclone II EP2C5 device to make a DSO/logic analyzer and I'm trying to figure out the max write rate I can use.
I'm using a configuration where LB,UB are low and OE is high so I'm just using low pulses on WE to control the operation, according to the datasheet the min width of a low WR pulse must be 8ns but I'm using 10ns.
I have used the PLL of the FPGA to generate two 90MHz clocks , the second one is shifted by 324 degree , this has allowed me to use a write cycle of about 11ns , for 10ns WR is low and for 1ns high
This is the post fit simulation result
My question is do you think it is possible for this to actually work in hardware (I don't have the FPGA in hand), the 1ns pulse seems too small and I'm not sure that the FPGA would be able to produce it in the the output or if it wouldn't reach the RAM (PCB and RAM limitations?) or maybe the RAM would need more than that.
According to the RAM datasheet the min duration of the WR low pulse can be 8ns so maybe I can make the pulse 8ns low and 3ns high or if that wouldn't work either what pulse durations would you suggest?
Alex
I'm using a configuration where LB,UB are low and OE is high so I'm just using low pulses on WE to control the operation, according to the datasheet the min width of a low WR pulse must be 8ns but I'm using 10ns.
I have used the PLL of the FPGA to generate two 90MHz clocks , the second one is shifted by 324 degree , this has allowed me to use a write cycle of about 11ns , for 10ns WR is low and for 1ns high
This is the post fit simulation result
My question is do you think it is possible for this to actually work in hardware (I don't have the FPGA in hand), the 1ns pulse seems too small and I'm not sure that the FPGA would be able to produce it in the the output or if it wouldn't reach the RAM (PCB and RAM limitations?) or maybe the RAM would need more than that.
According to the RAM datasheet the min duration of the WR low pulse can be 8ns so maybe I can make the pulse 8ns low and 3ns high or if that wouldn't work either what pulse durations would you suggest?
Alex