FPGA receice LVDS signal

[timedate]

Hi, all

I am using Altera Cyclone lV to receive the "LVDS" data from a clock and data recovery (ADN2813)

Below is my schematic,.



what I did in the PFGA is, let the pin work as "LVDS" or "LVDS bus", like below:




I can successfully receive the data. see "y7" and "rx", they are exactly the same(except the delay).



However, in the logic analyser, I found that, the signal would be suddenly comes to zero for a very short time. like blew.




Does anybody have idea, where this suddenly ZERO comes from? am I configure the FPGA as LVDS receiver correctly?

Besides, the LVDS signal is totally fine in the oscilloscope.

Thanks in advance.

 

[ads-ee]

main_new:inst|rx is directly off the lvds input buffer?

Maybe you should post the code for the lvds interface.

 

[timedate]

Hi， ads-ee

Thanks, I just solve the problem. Before, I forget to connect the gnd of the FPGA to LVDS gnd....