FPGA oscillator ring implemented

[shaiko]

Following my prior posts about making an asynchronous design synchronous - I implemented a ring oscillator on the Actel IGLOO FPGA. the results are rather strange.

This is my hardware :

library ieee ;
	use ieee.std_logic_1164.all ;
	use ieee.numeric_std.all ;

entity ring_oscillator is                                                                                 
	generic
	( 
		chain_width : natural range 1 to 1000 := 50 -- must be an even number
	) ;                                        																					
	port
	( 
		RESET_I : in std_logic ;
		RING_OSCILLATOR_GENERATED_CLOCK_O : buffer std_logic 
	) ;	                                                                                                                          
end entity ring_oscillator ;

architecture synthesizable_ring_oscillator of ring_oscillator is	   

	signal chain : unsigned ( chain_width downto 0 ) ;
	
	attribute syn_keep: boolean;
	attribute syn_keep of chain : signal is true;
	  
begin

	logic_chain : for i in 1 to chain_width 
	generate
		chain ( i ) <= chain ( i - 1 ) ;
	end generate;
	chain ( 0 ) <= not chain ( chain_width ) or ( not RESET_I ) ;		

	t_flip_flop : process ( RESET_I , chain ( 0 ) )
	begin
		if RESET_I = '0' then
			RING_OSCILLATOR_GENERATED_CLOCK_O <= '0' ;
		elsif rising_edge ( chain ( 0 ) ) then
			RING_OSCILLATOR_GENERATED_CLOCK_O <= not RING_OSCILLATOR_GENERATED_CLOCK_O ; 
		end if ;	
	end process t_flip_flop ;	

end architecture synthesizable_ring_oscillator ;

The output is a nice trapezoidal waveform but for some reason changing the "chain_width" generic (from 50 to 150) had no effect on the generated clock's frequency(!)
Modifyng the code by adding additional T flip - flops did however divide the frequency further.
Any ideas ?

 

[std_match]

What frequency do you get from the ring oscillator?
Are you sure that most of "chain" has not been optimized away?
It is a waste of resources to use hundreds of buffers in "chain". When you come down to a "safe" frequency, it is better to reduce the frequency further by using flip-flops.

 

[shaiko]

What frequency do you get from the ring oscillator?

Arount 66MHz

Are you sure that most of "chain" has not been optimized away?

Not sure. But as you can see, I did use the "keep" attribute.

It is a waste of resources to use hundreds of buffers in "chain".

I understand that - I wanted to see if my generic code works. But changing the number of loops seems to have no effect.

 

[FvM]

I would primarly review the gate level netlist to understand, if the intended hardware has been generated.

As previously reported, the same construct is working well with Quartus and Altera FPGAs.