FPGA Nested Modules issues - help needed

[dlh]

FPGA Module issues

Hey,

I am pretty new to FPGA. I am confused about the program 'flow' in verilog.. What I want is to have a module with nested modules. Like:

module large( a, b, c, d, out)
    multiply (a,b, out1)
    multiply (c,d, out2)
    out = out1 - out2
    multiply(out, d, out);
end module

I am confused how I can do this. I don't want the multiply modules to be new instances - I want the one multipy module to do all 3 multiplications sequentially as I want to save room on the fpga. How do I go about doing this. In general I am confused about how to make things run in parallel vs sequentially... Any info would be much appreciated!

Thanks