Pedro23
Newbie level 2
fpga memory
Dear all,
I try to design memory to work as a buffer for the input datas. I work on a board spartan3E.
My input datas are 4 channels std_logic_vector(11 downto 0), frequency 50 MHz.
I'm thinking to use one FIFO per channel, a MUX 4->1 and a single RAM. I need to speed up the reading frequency of FIFOs, to spare the RAM in 4 (one channel=one part).
Maybe i can use core generator from xilinx to generate FIFOs and RAM...but i don't know how to choose the depth and width of FIFOs/RAM, the reading frequency of FIFOs (200 MHz?), how to control the data exchanges...
Finally, i have ideas but i have difficulties to implement the solution.
Someone can help me?
Thank you!
Dear all,
I try to design memory to work as a buffer for the input datas. I work on a board spartan3E.
My input datas are 4 channels std_logic_vector(11 downto 0), frequency 50 MHz.
I'm thinking to use one FIFO per channel, a MUX 4->1 and a single RAM. I need to speed up the reading frequency of FIFOs, to spare the RAM in 4 (one channel=one part).
Maybe i can use core generator from xilinx to generate FIFOs and RAM...but i don't know how to choose the depth and width of FIFOs/RAM, the reading frequency of FIFOs (200 MHz?), how to control the data exchanges...
Finally, i have ideas but i have difficulties to implement the solution.
Someone can help me?
Thank you!