FPGA: Memory buffers design in VHDL

[Pedro23]

fpga memory

Dear all,

I try to design memory to work as a buffer for the input datas. I work on a board spartan3E.
My input datas are 4 channels std_logic_vector(11 downto 0), frequency 50 MHz.
I'm thinking to use one FIFO per channel, a MUX 4->1 and a single RAM. I need to speed up the reading frequency of FIFOs, to spare the RAM in 4 (one channel=one part).
Maybe i can use core generator from xilinx to generate FIFOs and RAM...but i don't know how to choose the depth and width of FIFOs/RAM, the reading frequency of FIFOs (200 MHz?), how to control the data exchanges...
Finally, i have ideas but i have difficulties to implement the solution.

Someone can help me?
Thank you!

 

[xtcx]

vhdl memory

Hello Pedro,
Before you begin, you must be sure about the input data frequency or the bit rate. Use of FIFO means so much only when you have variable Bit rate. Or else,you will eventually end up with fifo shortage and lose data...Check this link for some info on fifo details and calculation before you start....And try to provide little more info....
<http://www.asic-world.com/tidbits/fifo_depth.html>
Regards

 

[Pedro23]

vhdl+memory

Hello xtcx,

I try to make a data acquisition system. The datas leave an ADC on 4 LVDS channels by 12 bits frame. Then, i do a conversion serial to parallel. I'm sure about my input: the data come by frame of 12bits at the frequency 50Mhz, so it's 600Mbps at the FIFO input.
I chose FIFOs with independent clocks and i think a 200Mhz reading frequency could be enough.
I have already seen this calculation method for the FIFO depth but it seems confused for me...

 

[xtcx]

8 bit fifo vhdl

Hi Pedro,
Your concept is still unclear to me..Your ADC updates every 50MHZ only,are you sure about that?....Ok,so for readinf 4-channels,your read speed should be 200MHz.....Altogethor,you wouldn't be needing a fifo if your switching speed is 4 times faster than input data speed,provided your RAM should be capable of writing data at such speeds. For eg., in my design, I get 8-bit data from 8 different inputs. But I can only process or allow one channel(8-bit) at one time. In this case, I never opt for fifo because the reason is all data bits from 8 channels are at constant bit rate of 128Kbps. So
8 ch x 128KHz = 1024KHz.
So If I switch the MUX's Sel at a speed of 1024KHz, then I can read all 8-ch without any loss. Also my RAM has 8-bit data width and I simply change the address of my RAM for 8 channels using the current value in my selector. For eg., if my selector has value 5(ch-5),then I will add this 5 with ram addr.Well, In your case,
4ch x 50MHZ = 200MHz.
So if you rapidly switch the selector of your 4 to 1 mux in 200MHZ speed,you will not lose any data at the output of mux. You must configure your RAM to data widths of 12-bit. You can simply change the address of your RAM depending on your MUX selector value. Just make sure you write the data in RAM at speeds of 200MHZ. Final thing is,I don't see if there is any need for FIFO at all in your case.....except You only need a FIFO if writing RAM at this speed is not possible in case such as 133MHz RAM or even slower....Is it clear now?...