beetlejuice
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Hi BarryPersonally, I would prefer the parallel approach. With proper layout and cabling, I wouldn’t worry too much about EMC. Can your FPGA (which one?) even handle 320 MHz inputs?
Assuming that I can keep the LVDS Data and LVDS Clock wire pairs the same length (which over just 500mm should not be too problematic) then isn't is possible just to use the source (lvds) clock, to clock the data bits into the FPGA and to also clock the serial to parallel logic, then that parallel output would feed into an asynchronous FIFO where it will exit in the system FPGA clock domain.In either case parallel or serial, you will need to use whatever support the ECP5 has to phase shift either the clock or data to capture the data using the source synchronous clock input.
I've been doing exactly that. It seems that there is plenty of documentation for implementing high speed DDR interfaces but little for SDR. However I did find a piece tucked away in a document that explained exactly what I needed - a GIREG_RX.SCLK interface implemented in one of the PIO cells. Problem is that the maximum clock frequency is just 200MHz and I need 320MHz.You should look around the Lattice website and look for any app notes on source synchronous interfaces, or example designs that use a source synchronous interfaces. That would show you how to implement such interfaces in an ECP5.
That's an interesting suggestion. The clock comes straight from the MY9V034 camera chip so would need an external high frequency divider or PLL, but it seems possible.Can you divide the clock to 160 MHz and use the DDR functionality in the FPGA?
Not sure why you’re so resistant to 4 parallel interfaces. It’s done all the time; why are you so concerned with EMI? Adding four FPGAs to the string just decreases reliability, adds complexity and cost and development time.
And i wouldn’t totally dismiss the serial interface yet. You could just write some code that implements the serial interface, and see if it compiles and meets timing.
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