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FPGA Low Power Design

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ldm

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Does 'FPGA Low Power Design' sound strange? If not, what techniques should be used? Are the techniques similar to ones, which popular in ASIC Low Power designs (gated clocks, etc.) or there any specific?
 

satya_422

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hello u can use this thesis report




ldm said:
Does 'FPGA Low Power Design' sound strange? If not, what techniques should be used? Are the techniques similar to ones, which popular in ASIC Low Power designs (gated clocks, etc.) or there any specific?
 

satyakumar

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Hi,
there are some similarities between asic low power design and fpga low power design. If u take interms of algoritham level i think both cases are same, but interms of implementation at circuit level there are some differences in terms of decoding the FSM and routing of different combinational blocks.
Combinational blocks in FPGA are implemented using LUT aswell as using Gates, The LUT based approach takes less delay. Where as in ASIC the design is based on standard cells and there delay and area are fixed. mostly controlled by routing stratagies by reducing some constraints on the design.
 

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