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FPGA Implementation Verification

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venkatesh27989

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hello... am supposed to implement a 8051 open core (verilog programming) into a Xilinx spartan 3e (xcs3500e) board and verify the implementation with led blink program.. i have implemented the core into the fpga successfully though ISE and iMPACT...

My question is how can I load the blink program into the device?? This blink program acts as the final verification for my implementation!!

Thanks a lot...
 

ninju

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Use the RAM to load your program. Some mapping has to be done. I haven't tried this in Xilinx, only Altera.
 

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specifically you'll have to load (initialize) the RAM the 8051 core uses as its instruction memory.
 

venkatesh27989

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specifically you'll have to load (initialize) the RAM the 8051 core uses as its instruction memory.

Thanks for your reply!! As far as what I understood, RAM can be initialized through .coe file... But I have difficulty with instantiation process...
Any help with that??
 

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So you haven't instantiated the RAM yet?
Well instantiate a coregen RAM with the .coe file used to initialize it.

Or is it you don't know how to get the .coe file into the RAM?
If you used coregen to build the RAM there should be an option to read a .coe file to initialize the RAM. Then just rebuild your project.
 

venkatesh27989

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No I still haven't instantiated it... i have the .coe file with me... i tried generating a blocked memory by choosing this .coe as an Init File... Now I have a blk_mem_gen (.xco file) that is added in the ISE source list...
What I did till now is right? If so what should I do next?
 

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Instantiate it in the top level file and hook it up to your 8051 core.

Assuming you have a top level file...you didn't just compile the 8051 core directly as the top level did you?

If you don't have a top level file now is the time to create one :)...

And as you seem to be very new to this stuff (forgive me if you already know this stuff)...
make constraint files for the design (i.e. .ucf and an .xcf if you're using XST).
At a minimum the .ucf should have the timing constraints for your design along with any pin placement information. The .xcf can just have the timing constraints. I usually have multiple timing constraint files one for the timing and the second for physical stuff like pin placements and I/O standards.
 

venkatesh27989

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I already have a top module which is the oc8051_top.. okay I will try instantiating the ram into it...

And as you told me about the .ucf and .xcf... Am already done with all of that... I just wanted to create the Block Memory as a Post Synthesis process!!
 

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