Looking at this code, I suggest you go and start a course on digital logic.
This code is no more than a testbench for a design. There are many problems with this design.
1. There are no inputs or outputs, only a clock. This design will synthesise to nothing.
2. You cannot do file IO on an FPGA. VHDL file IO is for testbenches only.
3. You cannot use real types.
The big issue is the first one. You have written this code like software. VHDL is a description language, NOT a programming language. I suggest you delete all this code, draw the circuit you're tryiung to produce on a piece of paper, and only when you've done that, start the VHDL again.