FPGA implementation for image compression

[chitra ranganath]

hi
i have written a vhdl code for image compression n i have simulated using modelsim too. if i have to implement on fpga wat is that i need to do. i really have no knowledge of FPGA. i jus want to know do all thae programs which are simulated are eligible for FPGA implementation ????? or wat is the requirement for a vhdl code to be implemented on FPGA

 

[TrickyDicky]

Have you followed all the coding guidlines? You can write code that will simulate correctly, but if you have not followed any coding guidlines for synthesis you have no chance of getting it on an FPGA. Without seeing your code I have no idea if it will work.

To get it on an FPGA you need whichever vendors compiler tools (ISE for Xilinx, Quartus for Altera), create a project, assign all your pins and away you go.

 

[chitra ranganath]

in my vhdl code i synthesized but i`m left wid an error that signal<> of type real not supported.. n simulation i carried out using modelsim. i`m gettin the expected result. but how to overcome this error of signal pf type real???? the expected result in my code needs to be floating point number only.

 

[TrickyDicky]

There is no problem using real type in simulation. it is just that, a Simulation.
When you compile for an FPGA, real type is not supported because there is no definition on how it works in terms of bits.

The ONLY solution is to re-write your code where you have used the real type and replace all real types with std_logic_vector and floating point IP blocks. There is no other solution.

I would not recommend using floating point at all though. Fixed point is far more appropriate in an FPGA.

 

[chitra ranganath]

i`m assigning real for a ratio in my code. so if the ratio comes around 2.187, n i`m using std_logic_vector how far is it justified???

 

[TrickyDicky]

Why dont you post the code where it is used. If its in the executable part of the code, you cannot use it.

Look into how to use fixed point.

 

[chitra ranganath]

shall i post my code

---------- Post added at 09:07 ---------- Previous post was at 09:04 ----------

i just want to make my code to be implemented on fpga. or i can say it must be a code which is eligible to be implemented on fpga

 

[TrickyDicky]

Post the code.

But you cannot use real in FPGA code.

 

[chitra ranganath]

here is the code

 

[chitra ranganath]

fine sir i don`t use but wat can be a substitute. like jus now i thot of integer atleast. but we i changed to integer i`m gettin other error like bad condition in wait statement or only one clock per process

---------- Post added at 09:18 ---------- Previous post was at 09:17 ----------

i`ll post even text file in 2min

 

[TrickyDicky]

Looking at this code, I suggest you go and start a course on digital logic.

This code is no more than a testbench for a design. There are many problems with this design.

1. There are no inputs or outputs, only a clock. This design will synthesise to nothing.
2. You cannot do file IO on an FPGA. VHDL file IO is for testbenches only.
3. You cannot use real types.

The big issue is the first one. You have written this code like software. VHDL is a description language, NOT a programming language. I suggest you delete all this code, draw the circuit you're tryiung to produce on a piece of paper, and only when you've done that, start the VHDL again.

 

[chitra ranganath]

the locations of these files need to be changed at lines 84 n 85 n 86

 

[chitra ranganath]

k sir thanks for the suggestion
will start frm now

---------- Post added at 09:29 ---------- Previous post was at 09:26 ----------

how can i give those contents in text file as input if file io cannot be done on fpga.

 

[TrickyDicky]

via some Input method that you will need to either write a controller for, or get some ip.

Eg. RS232 (fairly easy)
Ethernet (hard to write)
USB (very hard to write)