FPGA GPIOs pulldown resistor

[KingMoshe]

Hi all,
Is there a good reason to connect all unused GPIOS to pulldown resistor?

Thanks.

 

[FvM]

May be, depending on the used FPGA and its IO features. I'm e.g. using internal weak pull-up for unused GPIO as default setting with Intel FPGA. You generally want to avoid floating inputs.

 

[KlausST]

Hi

There is a reason ... that says: never leave a (unused) input floating.

Usually FPGAs have the option to drive pullups/pulldown on I/Os internally.

So generally there is no need for external resistors .... unless they are used for signals that need to keep a dedicated level before they are properly configured.

Klaus

 

[KingMoshe]

Hi

There is a reason ... that says: never leave a (unused) input floating.

Usually FPGAs have the option to drive pullups/pulldown on I/Os internally.

So generally there is no need for external resistors .... unless they are used for signals that need to keep a dedicated level before they are properly configured.

Klaus

Thanks,
These GPIOs do not need to keep any value before they are properly configured because they are unused in my FPGA logic.
So it enough to use internally pull up/down ?

 

[FvM]

FPGAs may not provide internal pull-up/-down for all pins, e.g. dedicated clock inputs. In case of doubt, there's a pin connection guideline in the manufacturer documentation with suggestion for all pin classes.