FPGA & Gated Clock

[ivlsi]

Hi All,

Why implementation of the Gated Clock @FPGA is a problem (almost impossible as I was told in the interview)?

Thank you!

 

[barry]

1) It's a problem because you are adding a delay to the clock path and also might introduce glitches.
2) what do you mean it's impossible? If it's impossible, it's not a problem!!

 

[FvM]

FPGA clocks are distributed by dedicated routing resources. You can't interpose additional gating logic without affecting it's timing performance. Some FPGAs have dedicated clock control blocks to switch or gate clocks, in so far the original statement isn't completely true.

 

[ivlsi]

FPGA clocks are distributed by dedicated routing resources. You can't interpose additional gating logic without affecting it's timing performance. Some FPGAs have dedicated clock control blocks to switch or gate clocks, in so far the original statement isn't completely true.

how big these clock control blocks? How many clocks might be gated?

Anyway, I think that the problem is due to the fact that clock trees are already built in FPGAs and don't allow any intervention.

 

[barry]

What do you mean, "How big"?

And what do you mean "the problem is due to the fact that clock trees are already built"? Which problem?

 

[ivlsi]

What do you mean, "How big"?

I meant "how many clock domains might be controlled".

And what do you mean "the problem is due to the fact that clock trees are already built"? Which problem?

In ASIC clock trees are built after all logic is implemented (placed and routed) with gates, etc. In FPGA clock trees are implemented without taking in account how the LUTs will be routed and connected one with another. Gated clocks usually introduce delays (aka skew, latency) on the clock. There is no way to balance the clock trees then. So, a synchronous design becomes an asynchronous one (clocks are not balanced/synchronized one with another) that may introduce timing problems and as a result logical errors.
Disclaimer: I'm not a FPGA designer. So, all written above is just a guess and should be approved by professionals ;-)

 

[barry]

The number of clock domains you can control is totally dependent on the device you are using.

Even with a gated clock it's still synchronous. But, as you point out, you have introduced additional delay in the clock path which can affect meeting timing, and, depending on how you use the gate, you can generate glitches.

 

[ivlsi]

depending on how you use the gate, you can generate glitches

Usually Negative Latch with AND Gate are used to gate the clock. Is there a way to mange their timing in order to prevent glitches? Since gating is done on the negative edge of the clock, there is 1/2 of clock period a a margin. Why glitches?

 

[barry]

How do you control "gating done on the negative edge"? If you can guarantee that condition, then fine, but if your gate signal is asynchronous then you can get into trouble.

 

[Analog Ground]

Some devices, such as Altera Cyclone, have the capability to originate a clock from the logic array in addition to the more usual way of originating from a dedicated input pin. So, this allows the clock to be gated. Now, to be fair, this gates the clock to ALL the logic elements using that clock distribution. What is not done is to gate clocks to individual logic elements. This would make it very difficult to analyze the timing between LEs with and without the gated clock.