fpga design problems....???

[nilusharief003]

You use Tcl commands like this:

set_instance_assignment -name VIRTUAL_PIN ON -to my_pin

Read more in page 15-11 in volume 2 of the Quartus II Handbook:

https://www.altera.com/literature/hb/qts/qts_qii5v2.pdf

Here are a few lines from the chapter:

"Virtual Pins

Usually, when you compile a design in the Quartus II software, all I/O ports are mapped directly to pins on the targeted device. However, you may not want to map all I/O ports to the device pins; use the Virtual Pin assignment then.
A virtual pin is an I/O element that you do not intend to connect to the chip pins. You create a virtual pin by assigning the Virtual Pin logic option to an I/O element. When you compile a design with some I/O elements assigned as virtual pins, those I/O elements become mapped to a logic element and not to a pin during compilation, and are then implemented as a LUT. You might use virtual pin assignments when you compile a partial design, because not all the I/Os from a partial design may drive chip pins at the top level."

hi sir i tried in quartus with virtual pins n i got ans............thk uuuuuu very much.......

 

[TrickyDicky]

vitual pins are just a way for you to get an idea of resource usage for a single entity. You cannot get a working design using vitual pins.

 

[nilusharief003]

vitual pins are just a way for you to get an idea of resource usage for a single entity. You cannot get a working design using vitual pins.

sir..thr is a provision in software where we cn give values for virtual pins as either on or off...ie..1 or 0...
with sme pins as input n sme as output n rest all as virtual cnt we get ans????
whether this ll b right or nt???

 

[TrickyDicky]

you would do that by connecting the inputs to 1 or 0. But this will have the effect of synthesising away large amounts of logic as the inputs are constant.

Virtual pins are not a solution to your integration problem. You still need a mecahnism to get the data in and out of the chip to allow your design to work.

 

[FvM]

I suggest to think of an interface, that would be also applicable to a real hardware design, e.g. a 32 or 64-Bit data bus with an address port to select individual registers and read and write strobes. Preferably as synchronous bus with a common clock.