Never heard of it, probably it doesn't.In Altera Quartus there is an alternative to a wrapper.
You can define "virtual pins", and then you can have more pins than the physical device.
I don't know if Xilinx has the same possibility.
OK, probably there's something I don't undestand. But sure as hell they did use some kind of top-level interface in their project.i hv exactly followed d architecture n datapath given in d ieee paper
A Highly Efficient Cipher Processor for Dual-Field
Elliptic Curve Cryptography
In Altera Quartus there is an alternative to a wrapper.
You can define "virtual pins", and then you can have more pins than the physical device.
This only solves the compilation problem. You still need a wrapper if you want to download the design into a device.
With virtual pins you can compile a sub-block as a Quartus top-level entity, even if it has "too many" pins. This is good for large designs when you don't want to compile the whole design every time.
I don't know if Xilinx has the same possibility.
You use Tcl commands like this:
set_instance_assignment -name VIRTUAL_PIN ON -to my_pin
Read more in page 15-11 in volume 2 of the Quartus II Handbook:
https://www.altera.com/literature/hb/qts/qts_qii5v2.pdf
Here are a few lines from the chapter:
"Virtual Pins
Usually, when you compile a design in the Quartus II software, all I/O ports are mapped directly to pins on the targeted device. However, you may not want to map all I/O ports to the device pins; use the Virtual Pin assignment then.
A virtual pin is an I/O element that you do not intend to connect to the chip pins. You create a virtual pin by assigning the Virtual Pin logic option to an I/O element. When you compile a design with some I/O elements assigned as virtual pins, those I/O elements become mapped to a logic element and not to a pin during compilation, and are then implemented as a LUT. You might use virtual pin assignments when you compile a partial design, because not all the I/Os from a partial design may drive chip pins at the top level."
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