FPGA design flow comparison with ASIC design flow

[carrot]

FPGA design flow

Hi
Can anyone help me in giving the correct FPGA design flow comparing with that of a ASIC design flow.

 

[arunragavan]

Re: FPGA design flow

take a look at this

h**p://www.klsi.com/ASIC/design.html

with regards,

 

[andonie12]

Re: FPGA design flow

Hello there,

From the Start:

1) Write VHDL Code using SlickEdit
2) Compile the VHDL Code using ModelSim Software
3) Use Xilinx Software to download the VHDL Code.

After Step #3 then the FPGA Flow will be in Xilinx Software

1) Synthesis the VHDL Code
2) Implement the VHDL Code
3) Generate a "bit file" to download into the FPGA

Need more help let me know

 

[gknerd]

Re: FPGA design flow

For a complete FPGA design flow, you can take a look at the Xilinx ISE 6 In Depth Tutorial:

**broken link removed**

 

[sp]

Re: FPGA design flow

here is the fpga article......

http://www.tu-harburg.de/~simz0218/cpd/Design_Flows%20for%20the%20Microelectronics%20Industry.pdf

or the same location.....

http://www.tu-harburg.de/~simz0218/cpd/

it can b found in edaboard....