Hey Guys,
It's been a month since I last posted. I've found alot of people suggesting VHDL lines of code as a good sizing metric for the entire development effort, from requirements defintion all the way through testing. I hear that many designers have a good feel for how many lines of code a project will need from an early stage. Of course the effort-per-line-of-code depends on alot of things. I was thinking of having the cost/effort estimation equations that look something like this:
Functional Spec = f(VHDL lines of code, Logic Complexity)
Architectural and Detailed Design = f(VHDL LOC, Logic Complexity)
Simulation, Verification, Implementation = f(VHDL LOC, Logic Complexity, expected timing issues (based on clock speed, how highly pipelined the design is, etc))
Floorplanning, Place and Route = f(VHDL LOC, expected timing issues)
Those would be the basic cost drivers for each activity, though there are many other drivers that i'll fit in somewhere (amount of reuse, experience of the team, etc.) Does this seem like a good approach?