Oct 31, 2007 #1 N nicoxp31 Newbie level 6 Joined Oct 3, 2007 Messages 12 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location France Activity points 1,440 fpgaclk Hi, I just wanted to know if they were any danger about multiplexed clock in a FPGA design: for instance: assign clk_o = tx_sel ? tx_clk_i : rx_clk_i; Can this generate instability then? Thanks, Regards, Jerome
fpgaclk Hi, I just wanted to know if they were any danger about multiplexed clock in a FPGA design: for instance: assign clk_o = tx_sel ? tx_clk_i : rx_clk_i; Can this generate instability then? Thanks, Regards, Jerome
Oct 31, 2007 #2 K kanagavel_docs Member level 1 Joined Aug 18, 2007 Messages 41 Helped 8 Reputation 16 Reaction score 1 Trophy points 1,288 Location Chennai Activity points 1,522 clk multiplexing Hi, There will not be smooth transition b/w clocks. Synthesis tool will not do the STA properly because of the gated clock. The best way to do this is implement the logic as shown. Regards, Kanags
clk multiplexing Hi, There will not be smooth transition b/w clocks. Synthesis tool will not do the STA properly because of the gated clock. The best way to do this is implement the logic as shown. Regards, Kanags
Oct 31, 2007 #3 T tom_hanks Full Member level 5 Joined Aug 28, 2003 Messages 243 Helped 14 Reputation 28 Reaction score 1 Trophy points 1,298 Activity points 1,571 i will suggest use the pll at the o/p of mux...
Oct 31, 2007 #4 N nicoxp31 Newbie level 6 Joined Oct 3, 2007 Messages 12 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Location France Activity points 1,440 Sorry but i do not understand how your schematic can improve the clock multiplexing since we are still using logic behind !
Sorry but i do not understand how your schematic can improve the clock multiplexing since we are still using logic behind !
Nov 1, 2007 #5 H huster Junior Member level 3 Joined Jun 4, 2001 Messages 26 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Activity points 86 you can use bufgmux to implement the clock mux function if you use Xilinx' FPGA