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[FPGA] Clk Multiplexing

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nicoxp31

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fpgaclk

Hi,

I just wanted to know if they were any danger about multiplexed clock in a FPGA design:

for instance:
assign clk_o = tx_sel ? tx_clk_i : rx_clk_i;

Can this generate instability then?

Thanks,
Regards,
Jerome
 

kanagavel_docs

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clk multiplexing

Hi,

There will not be smooth transition b/w clocks.
Synthesis tool will not do the STA properly because of the gated clock. The best way to do this is implement the logic as shown.



Regards,
Kanags
 

tom_hanks

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i will suggest use the pll at the o/p of mux...
 

nicoxp31

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Sorry but i do not understand how your schematic can improve the clock multiplexing since we are still using logic behind !
 

huster

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you can use bufgmux to implement the clock mux function if you use Xilinx' FPGA
 

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