FPGA based ATE (Automatic Test Equipment)

[jenish]

I am on a starting phase of designing low cost ATE based on FPGA.
Basic idea is the STIL file which contains signal vectors fed in to proposed FPGA which will drive DUT.
I got glimpse of FPGA which running on PYNQ ( ZYNQ series , By Xilinxs ) from internet search, hops can able connect STIL files to Python library ( Semi-ATE-STIL, not sure this suited for me).
Please give your recommendations, whether this approach is fair or any alternative methods.

 

[dick_freebird]

While an FPGA may serve to throw functional vectors and maybe
criticize as well, product acceptance testing also requires timing
and parametric (I, V, R/Z) testing which are best done with other
resources I expect. FPGA outputs are probably unsuited for
voltages outside I/O rails, you could lash up some ADC / DAC /
programmable gain resources outside I suppose. Perhaps you
can create timing measurement inside the FPGA (presuming
that you need less precision than the raw or internal-PLL clock
period).

Are you planning to restrict force and expect vectors to the on
chip memory? If using too many "bolt-ons" you may end up
better off with a processor and baggage, than a FPGA and
baggage. Since you'll still need a way to tell the FPGA anyhow.

 

[jenish]

While an FPGA may serve to throw functional vectors and maybe
criticize as well, product acceptance testing also requires timing
and parametric (I, V, R/Z) testing which are best done with other
resources I expect. FPGA outputs are probably unsuited for
voltages outside I/O rails, you could lash up some ADC / DAC /
programmable gain resources outside I suppose. Perhaps you
can create timing measurement inside the FPGA (presuming
that you need less precision than the raw or internal-PLL clock
period).

Are you planning to restrict force and expect vectors to the on
chip memory? If using too many "bolt-ons" you may end up
better off with a processor and baggage, than a FPGA and
baggage. Since you'll still need a way to tell the FPGA anyhow.

Thanks for your reply,
I know, FPGA can handle Digital signals. Additional circuitry required to handle tests involving current (I) parameters.
My Idea is that, as beginning of project, only Digital vectors handled by proposed FPGA.

The reason I choose FPGA for the development, User interface of ZNYQ. You are right, a processor and memory bank sufficient for this operation. But GUI development need different expertise.
Thankyou for your suggestion.

 

[ThisIsNotSam]

There is some academic research on how to build DIY ATEs from cheap components. There are even things like RF testers based on digital ATE. It's a hack, of course, but if done correctly can work.

 

[jenish]

There is some academic research on how to build DIY ATEs from cheap components. There are even things like RF testers based on digital ATE. It's a hack, of course, but if done correctly can work.

Thanks for your suggestion.
By the way, I am looking for specifically FPGA based solution. Because later same will scale up to generic ATE for ASICs. Currently trying to follow some IEEE papers, which are implemented FPGA base ATEs.