FPGA Advantage with Xilinx tools

[Giox]

fpga advantage 7.1

Hello everybody,
I'm trying to use the FPGA Advantage tools from Mentor Graphics in order to develop Xilinx FPGA based systems.
However at present time I'm not able to use the libraries of ISE Xilinx in Advantage.
IS there someone that can provide me some link to a document that explain how to integrate the libraries of ISE 7.1 in the Mentor Graphic tool (Windows version).
Thanks a lot, Giovanni

 

[Black Jack]

fpga advantage linking xilinx for synthesis

Hello everybody,
I'm trying to use the FPGA Advantage tools from Mentor Graphics in order to develop Xilinx FPGA based systems.
However at present time I'm not able to use the libraries of ISE Xilinx in Advantage.
IS there someone that can provide me some link to a document that explain how to integrate the libraries of ISE 7.1 in the Mentor Graphic tool (Windows version).
Thanks a lot, Giovanni

I can`t answer for you questions. But why FPGA Advantage?
I think that Synplify Pro give better results

 

[Giox]

fpga advantage xilinx

I chose Mnetor graphics because this is the first tools in my university and so my experience has born with them.
However I found the response for my question: iI have to integrate the coregen lib in FPGA Advantage as proposed in
h**p://www.saros.co.uk/hdlsolutions/ appsnotes/fpgaadvantage/UsingCoreGen.pdf

Hope this helps someone

 

[dainis]

fpga advantage xilinx programming file

I chose Mnetor graphics because this is the first tools in my university and so my experience has born with them.
However I found the response for my question: iI have to integrate the coregen lib in FPGA Advantage as proposed in
h**p://www.saros.co.uk/hdlsolutions/ appsnotes/fpgaadvantage/UsingCoreGen.pdf

Hope this helps someone

Remove space before appsnotes ....

 

[Giox]

fpgaadvantage synplify

I'm sorry, the link is:
h**p://www.saros.co.uk/hdlsolutions/appsnotes/index.shtml
(here are all the documents related with this topic)

 

[RemyMartin]

Nod. Synplify is better than Precision and Leo**do spectrum

 

[ljkong]

in fact i can understand what you mean .
which library do you want to use in ISE?
if you want to use coregen in FA, you can invoke the link in the task of hdl designer. but if you use ise7.1 and hdl designer is not the latest, you can not invoke coregen directly in FA..
in fact when you invoke coregen individually, it can generate two files . one is .vhd or .v and one is .edn. the .vhd or .v file is for simulation and the edn is for synthesis. you can import the .vhd into hdl designer, and modify the property of the module for synthesizing. then you can work rightly.
for simulation library ,you can run the command in MS's dos window.
the command is compxlib from xilinx.
for example:
compxlib -s mti_se -l vhdl or verilog -f all ;

then all the library can be compiled for simulation including simprims and unisim etc.
of course , you can create all coresponding library for unisims and xilinxcorelib in hdl designer. and then impporting the soure files into these library .the soure is in
directory /xilinx/vhdl or /xilinx/verilog.
then it is ok for everything.
mentor has many training materails. but i can not transfer it.
the internet is so slow.
or you can call mentor's AE. he can help you too.
good luck.