FPGA advantage 7.2, modelsim with systemC

mr_byte31 · Dec 26, 2008

modelsim with systemC

hi all
i have FPGA advantage 7.2
i want to simulate systemC module
how can i simulate it on modelsim
here is the code i want to simulate

//
// Created:
// by - Ahmed.UNKNOWN (AHMED)
// at - 02:39:23 26/12/2008
//
// using Mentor Graphics HDL Designer(TM) 2005.3 (Build 75)
//
#include<systemc.h>
SC_MODULE(new_top)
{
sc_signal<bool> reset;
counter_top top;
sc_clock CLK;
void sc_main_body();
SC_CTOR(new_top)
: reset("reset"),
top("top")
CLK("CLK", 10, SC_NS, 0.5, 0.0, SC_NS, false)
{
top.reset(reset);
SC_THREAD(sc_main_body);
}
};
void
new_top::sc_main_body()
{
reset.write(1);
wait(5, SC_NS);
reset.write(0);
wait(100, SC_NS);
reset.write(1);
wait(5, SC_NS);
reset.write(0);
wait(100, SC_NS);
}
SC_MODULE_EXPORT(new_top);

FPGA advantage 7.2, modelsim with systemC

mr_byte31

Full Member level 5

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FPGA advantage 7.2, modelsim with systemC

mr_byte31

Full Member level 5

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