Apr 25, 2018 #1 R rmk423 Newbie level 4 Joined Sep 1, 2017 Messages 7 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 52 Force in Synopsys DVE Hi, What is the difference between these two? 1) force a 0 2) force -deposit a 0 Please elaborate. Thanks, RMK
Force in Synopsys DVE Hi, What is the difference between these two? 1) force a 0 2) force -deposit a 0 Please elaborate. Thanks, RMK
May 3, 2018 #2 T Tieny Junior Member level 2 Joined Mar 18, 2017 Messages 24 Helped 1 Reputation 2 Reaction score 2 Trophy points 3 Location Viet Nam Activity points 125 Re: Force in Synopsys DVE 1) force a 0 -> Keep a constant 0 2) force -deposit a 0 -> Keep a constant until a change value by itself.
Re: Force in Synopsys DVE 1) force a 0 -> Keep a constant 0 2) force -deposit a 0 -> Keep a constant until a change value by itself.
May 31, 2018 #3 R rmk423 Newbie level 4 Joined Sep 1, 2017 Messages 7 Helped 0 Reputation 0 Reaction score 0 Trophy points 1 Activity points 52 Hi, I tried compiling a testbench.v with the below , but ended up with syntax error, force -deposit a = 0; How to do this? Thanks, RMK
Hi, I tried compiling a testbench.v with the below , but ended up with syntax error, force -deposit a = 0; How to do this? Thanks, RMK
May 31, 2018 #4 FvM Super Moderator Staff member Joined Jan 22, 2008 Messages 52,400 Helped 14,748 Reputation 29,778 Reaction score 14,093 Trophy points 1,393 Location Bochum, Germany Activity points 298,004 deposit is no known Verilog keyword. You are apparently confusing simulator command language with Verilog. - - - Updated - - - What do you want to achieve? An initial assignment or a assignment at a specific time?
deposit is no known Verilog keyword. You are apparently confusing simulator command language with Verilog. - - - Updated - - - What do you want to achieve? An initial assignment or a assignment at a specific time?
May 31, 2018 #5 ads-ee Super Moderator Staff member Joined Sep 10, 2013 Messages 7,944 Helped 1,822 Reputation 3,654 Reaction score 1,808 Trophy points 1,393 Location USA Activity points 60,207 Re: Force in Synopsys DVE rmk423 said: 1) force a 0 Click to expand... Modelsim/simulator do file command The equivalent in Verilog is Code: force a = 'b0; assuming a is in the same scope as the force command. rmk423 said: 2) force -deposit a 0 Click to expand... Simulator command with no direct equivalent statement in Verilog. Though you could potentially write code that emulates the functionality by checking for a condition that would result in releasing a force command and perform the release. Code: release a; // is used to end forcing a.
Re: Force in Synopsys DVE rmk423 said: 1) force a 0 Click to expand... Modelsim/simulator do file command The equivalent in Verilog is Code: force a = 'b0; assuming a is in the same scope as the force command. rmk423 said: 2) force -deposit a 0 Click to expand... Simulator command with no direct equivalent statement in Verilog. Though you could potentially write code that emulates the functionality by checking for a condition that would result in releasing a force command and perform the release. Code: release a; // is used to end forcing a.