Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Missing design modules on testbench error

Status
Not open for further replies.

michaelScott

Junior Member level 2
Joined
Mar 19, 2022
Messages
24
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
161
Hello friends,
While simulating a design wrapper file. I am getting a error messages as seen below. Despite all the modules names are correct in the wrapper file Why i am getting these errors. Can you help me about that.
Thanks i advance
 

Attachments

  • p2.jpg
    p2.jpg
    258.7 KB · Views: 132
  • p1.JPG
    p1.JPG
    42 KB · Views: 122

@michaelScott
1. It is typical Xilinx IDE, you should have posted this in the FPGA forum! Please take care about such stuff in the future.
2. This design has some kind of a BRAM which needs to be generated as a Xilinx IP, this is missing.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top