for loop inside a for loop

[ghostridergr]

Isn't allowed in VHDL? If not, how to implement it?

 

[bigdogguru]

Can you provide an example of the design you are attempting to implement?

BigDog

 

[ghostridergr]

Can you provide an example of the design you are attempting to implement?

BigDog

storing: for k in 0 to i loop
          
          inside: for l in 0 to j loop
            sum_of_square_all(k,l)<=signed(ext(sum_of_square(inp1(k),inp2(l),"000000000000000000000000"),3*N));
        end loop inside;

where i and j are variables, not signals.

 

[FvM]

- Neither the syntax of the inner nor of the outer loop is allowed in VHDL because the iteration range has to be a constant expression.
- It can be however done in VHDL by making a detour. Perform the iteration over the maximum range and use an if statement to select the actual range. It can also work in a nested loop.

Apart from the syntax problem, you should consider that a for loop in VHDL is a method to construct parallel logic, not generating a sequence in time. You easily get to the limits of availabe resources by using it in the way you do.

 

[ghostridergr]

- Neither the syntax of the inner nor of the outer loop is allowed in VHDL because the iteration range has to be a constant expression.
- It can be however done in VHDL by making a detour. Perform the iteration over the maximum range and use an if statement to select the actual range. It can also work in a nested loop.

Apart from the syntax problem, you should consider that a for loop in VHDL is a method to construct parallel logic, not generating a sequence in time. You easily get to the limits of availabe resources by using it in the way you do.

So what do you suggest me to do? What I want is to fill this 2d-array with results from my function call..

 

[FvM]

Use a construct like

for k = 0 to MAX_RANGE loop
  for l = 0 to MAX_RANGE loop
    if k<=i and l <=j then

    end if;
  end loop;
end loop;

 

[TrickyDicky]

- Neither the syntax of the inner nor of the outer loop is allowed in VHDL because the iteration range has to be a constant expression.
- It can be however done in VHDL by making a detour. Perform the iteration over the maximum range and use an if statement to select the actual range. It can also work in a nested loop.

This limitation only applies to synthesisable code, you can do it as much as you want in testbenches (and I regularly do to perform random wait times between data input, and random burst lengths).

So what do you suggest me to do? What I want is to fill this 2d-array with results from my function call..

If this is synthesisable code, you're going about it all the wrong way. Any array is probably going to be a memory, and you can only access 1 element of the array per clock cycle. You have to think in terms of the primitives - the memory only has 1 address input and one data in and out.

 

[ghostridergr]

This limitation only applies to synthesisable code, you can do it as much as you want in testbenches (and I regularly do to perform random wait times between data input, and random burst lengths).



If this is synthesisable code, you're going about it all the wrong way. Any array is probably going to be a memory, and you can only access 1 element of the array per clock cycle. You have to think in terms of the primitives - the memory only has 1 address input and one data in and out.

Thanks for your advice, they are really helpful for me that i am a little bit newbie.