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is nested for loop supported in verilog getting this error while using loop inside a for loop

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nomigul

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I am using ISE Design Suite 14.5 to try and synthesize a design and I keep getting the following errors while simulation behavioral model

Code:
Code:
module genvarexaplecode(a,b,y
    );
input [3:0]a,b;
integer mem[0:3][0:3];
output [1:0]y;

genvar i,j;
    generate
        for (i=0; i<4; i=i+1)
            begin
                for (j=0; j<4; j=j+1)
                    begin
                        assign mem[i-1][j-1] = a[i-1]*b[j-1];
                    end
            end
        assign y = mem[0][1]+mem[0][0];           
    endgenerate
endmodule


Error In Simulation:
Code:
ISim P.58f (signature 0x7708f090)
This is a Full version of ISim.
Time resolution is 1 ps
Simulator is doing circuit initialization process.
ERROR: In process genvar.vCont_33_0
FATAL ERROR:ISim: This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To search for possible resolutions to this issue, refer to the Xilinx answer database by going to http://www.xilinx.com/support/answers/index.htm and search with keywords 'ISim' and 'FATAL ERROR'. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
INFO: Simulator is stopped.
ISim>
 
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FvM

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Not a problem of nested loop.
Apparently ISim isn't designed to analyze the various errors in your code.

I notice these:
- mem must be of the net type, integer not allowed in this context
- index range error with [j-1]
- the compiler may require names for generate blocks

Did you try if ISE synthesis gives meaningful error messages?
--- Updated ---

I can compile the code after these edits (didn't think if it serves a useful purpose)
Code:
module genvarexamplecode(a,b,y
);
input [3:0]a,b;
wire mem[0:3][0:3];
output [1:0]y;

genvar i,j;
generate
for (i=0; i<4; i=i+1)
begin :gen1
for (j=0; j<4; j=j+1)
begin :gen2
assign mem[i][j] = a[i]*b[j];
end
end
assign y = mem[0][1]+mem[0][0];
endgenerate
endmodule
 
Last edited:

nomigul

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Not a problem of nested loop.
Apparently ISim isn't designed to analyze the various errors in your code.

I notice these:
- mem must be of the net type, integer not allowed in this context
- index range error with [j-1]
- the compiler may require names for generate blocks

Did you try if ISE synthesis gives meaningful error messages?
--- Updated ---

I can compile the code after these edits (didn't think if it serves a useful purpose)
Code:
module genvarexamplecode(a,b,y
);
input [3:0]a,b;
wire mem[0:3][0:3];
output [1:0]y;

genvar i,j;
generate
for (i=0; i<4; i=i+1)
begin :gen1
for (j=0; j<4; j=j+1)
begin :gen2
assign mem[i][j] = a[i]*b[j];
end
end
assign y = mem[0][1]+mem[0][0];
endgenerate
endmodule
I have checked the net type reg also but getting same error
 

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