For a CMOS inverter, the transition slope of Vout vs Vin DC

[santhosh.mandugula]

For a CMOS inverter, the transition slope of Vout vs Vin DC characteristics can be increased (steeper transition) by???
How it is related with W/L of PMOS and NMOS transistors of that inverter?

thanks in advance!!
santhosh

 

[electronrancher]

If the transistors are bigger (larger W/L) then they will be stronger, but will take more area.

 

[standup]

Re: For a CMOS inverter, the transition slope of Vout vs Vin

the transition time of inverter is related to the W/L ratio between PMOS and NMOS,VDD and the load capacitors.
Trise≈2C/(Kn*VDD)
Tfall≈2C/(Kp*VDD)
we can come to the conclusion that Trise<Tfall since the βn>βp.To get the same Trise and Tfall,to set Wp=βn/βp*Wn is the best choice.
It's obvious that the small load and large VDD lead to small Trise and Tfall,but the load is dominated by the whole circuit system.
hope it's helpful