Folded Cascode Op Amp question

[maxporter]

Hi all,

quick folded cascode question. Looking at some lectures slides, I stumbled upon the following slide/requirement:



It's the first comment. What would be the reason that I4 & I5 has to be 1.2 - 1.5 times I3? In other designs I noticed that they are mostly equal, I4=I5=I3. Also does the same rule apply for the differential PMOS variant?

Thanks in advance.

 

[erikl]

The answer is given in the first comment itself: I6 and I7 should never become zero.

wrong equation:
If I4=I5=I3, the current through M6..M11 would be zero, i.e. they wouldn't work.

correction:
If I4+I5=I3, the current through M6..M11 would be zero, i.e. they wouldn't work.

The same argument applies to the PMOS variant, of course.

 

[maxporter]

Ok, so this is the situation when I1 or I2 is carrying all of the current, right? Because if Vinm1=Vinm2, then I1=I2=I6=I7.

 

[erikl]

Ok, so this is the situation when I1 or I2 is carrying all of the current, right?

Yes.

... if Vinm1=Vinm2, then I1=I2=I6=I7.

This is only possible, if I4=2*I1 and I5=2*I2 . Why? Because I4=I1+I6 and I5=I2+I7 . As well as I1+I2=I3 .

 

[maxporter]

Ok, got it. Thanks for the insight and the quick replies.

 

[nitishn5]

You should try sweeping the currents I4 and I5 w.r.t. I3 and see at what offset voltage the circuit breaks. Put a voltage source at the gate to mimic a voltage mismatch.

You should ensure that I3 always takes away less current than what I4 and I5 provide so that there is current left over for the I6 and I7 even after accounting for mismatch. I3 is actively sinking current and will always demand current while I6 and I7 are more passive and will adjust the voltages to meet the demand.

I have faced a problem with robustness due to a similar issues.