If there is a large enough input voltage difference between vp and vn, all of I3 flows through either M1 or M2. This means that there is a current imbalance in the cascode stage, which is being levelled out by sinking/sourcing additional current to/from the output capacitor, which equals I3. So the fastest this can be done is I3/CL which translates to A/((A*s)/V) = V/s = Slew Rate.