Flyback Design_Problems

[treez]

Your turns ratio is 38.4:1 ..??
My secondary turns are:5
My Pri Turns are :51

woops , sorry I read your post #2 as lp="37mH" instead of "1.37mH"

 

[Bjtpower]

You need, 1k gate to source..! AND 22 ohm resistor to the gate, this will limit the VHF oscillations on the gate,,,!

Please find the attached schematics


As far Magnetic calculations are similar That i derived.
i got almost 122 uH AT 180-240V input Range,25v at 10 amp of output.

but i am trying the same for the 1.4mH of cores.

 

[treez]

Bjtpower:-
In post #11 you say NP=51, NS = 5
But in post #2, you say LP=1.37mH , LS=25uH

…this doesn’t add up.

NS/NP = SQRT(LS/LP)

So by your inductance measurements, your NP/NS = 7.4

- - - Updated - - -

also just noticed you are using a high side low side driver.....(si8234)
https://www.silabs.com/Support Documents/TechnicalDocs/Si823x.pdf

I think now we need to check if your duty is >50%, because you are using a half bridge driver....OK, its fine, your D=0.34 according to your pri/sec values of post#2, and considering your vin=180vdc and vout=12vdc

 

[c_mitra]

At 12V (13.8) and 10A out, try a 4.7 ohm 3W resistor and 200V 10nF cap (low loss film type)

I am not sure but it may be better to soften the turn on little slow. Perhaps a 12 ohm resistor with the same capacitor will reduce the ringing?

- - - Updated - - -

Hi Smijesh:

Hello c_Mitra,
I am using gate driver of 4 Ampere of silabs.

What is Turn on Hard n how to achieved..?

Why my Gate resistor Burnt.??

You are driving the gate fast to the saturation.

I now think that you need to soften the turn on: increase the gate resistance to 10-12 ohm and put a 0.01uF cap to the gate source. This will cause the turn on to be slowed down and more heat will be associated with each switch on/off but perhaps will be less compared to the the ringing.

 

[treez]

Here is an LTspice simulation of your flyback, as well as an excel spreadsheet which shows calculation of the rms currents etc….(attached)

I considered your spec is…
VIN=180-240VDC
VOUT=12V
IOUT=10A
FSW=100KHZ
LP=1.37mH
LS=25uH
k(transformer)=0.99


What type of diode are you using in the RCD clamp, be sure it is high enough voltage rated and ultra fast.

Please check your LP and LS with preferably a calibrated inductance meter and do the measurement at 100khz.

Also, please check your leakage inductance value, then you can do a rough 0.5*L(leak)*I(pripk)^2*freq type calculation to calculate the minimum power figure that gets dissipated due to the leakage.
In fact, the power dissipated in the RCD clamp will be more than 0.5*L*I^2*freq because of the fact that some of the primary power current gets “shovelled” into the rcd clamp before the secondary diode gets chance to turn on. Ill send you an brief article on this of you want.
You will need to check leakage inductance so we can see how much is likely to be dissipated.

Your secondary inductance is low compared to primary , so that means that the secondary referred leakage inductance will be low….which is at least a bit of good news for your snubbing of the secondary diode.

- - - Updated - - -

I would not add capacitors in the gate drive.
These can ring with stray inductances all over the place.
Just increase your gate series resistor if you want to slow the turn-on of the fet

 

[Bjtpower]

Bjtpower:-
In post #11 you say NP=51, NS = 5
But in post #2, you say LP=1.37mH , LS=25uH

…this doesn’t add up.

NS/NP = SQRT(LS/LP)

So by your inductance measurements, your NP/NS = 7.4

Are the calculations are rights..??
I checked the turns as well resistance and at the secondary it is 5 Turns & At primary it is 51 Turns.
also checked the inductance as well.

 

[treez]

what are your latest inductance figures>?, (at 100khz)
The inductances you have so far given don't add up to the ns/np = sqrt(ls/lp) equation

 

[Bjtpower]

what are your latest inductance figures>?, (at 100khz)
The inductances you have so far given don't add up to the ns/np = sqrt(ls/lp) equation

I have another transformer which i wound
Ns:5,Np:51
Lp:1.66mH,Ls:2uH

i am sure about the Turns ratio.

- - - Updated - - -

Here is an LTspice simulation of your flyback, as well as an excel spreadsheet which shows calculation of the rms currents etc….(attached)

I considered your spec is…
VIN=180-240VDC
VOUT=12V
IOUT=10A
FSW=100KHZ
LP=1.37mH
LS=25uH
k(transformer)=0.99

Kindly send your calculations.
I spreadsheet checked Which you forwarded.

Kindly send your calculation at max duty cycle will be 48%
Share your Email id.

 

[treez]

you can change the spreadsheet yourself if you wish, the one I sent you a few posts back

Most of you high current is in the secondary, so therefore you want the "secondary duty cycle" to be relatively larger than the primary duty cycle, so you do not want a duty cycle of 48%

- - - Updated - - -

again your above ns/np and ls/lp values don't correspond

 

[Bjtpower]

you can change the spreadsheet yourself if you wish, the one I sent you a few posts back

Most of you high current is in the secondary, so therefore you want the "secondary duty cycle" to be relatively larger than the primary duty cycle, so you do not want a duty cycle of 48%

- - - Updated - - -

again your above ns/np and ls/lp values don't correspond

Are the inductance values are collect
LP:122uH With N87 Material?

- - - Updated - - -

You need, 1k gate to source..! AND 22 ohm resistor to the gate, this will limit the VHF oscillations on the gate,,,!

A smaller value for Lpri (bigger core gap) will get you closer to DCM, discontinuous operation, which is better for the o/p diode and for generating RFI....!

- - - Updated - - -

plugging in the values for just DCM operation (@180VDC in min, 130W) gives L opt = 200uH, Ipk = 3.6A, 100kHz, Ton = 4uS (max).

Using these will give you best operation. For Iout = 10A average, Ipk = 40A, so large high quality electrolytics needed to soak up the current peak & ripple... say 5 x 470uF at a minimum.

Kindly share the formulas

 

[treez]

if you want to do dcm flyback, then your guiding formula is 0.5*L(pri)*[I(pripeak]^2*freq = input power

I take it you know formulae like V=Ldi.dt
also the formulae for trapezoid rms

- - - Updated - - -

Are the inductance values are collect
LP:122uH With N87 Material?

what inductance did you measure?

 

[E-design]

Kindly send your calculation at max duty cycle will be 48%

If you only allow a max duty cycle of 48%, it looks like you will have a problem at low line input.

The closest I can come to this is with using a standard ETD 44/ N87 (with an off-the-shelf 0.5 mm gap) will need 56% at 180 V and 42% at 240 V.

With ETD 34/ N87 (1 mm gap) pushes it to well over 60%.

What is the max V(ripple) you can tolerate on the output?

 

[treez]

Vout is 12v, and vin is 180-240vdc and pout=120w.
Therefore, there is far more rms current in the secondary.
As such, to reduce secondary rms as much as possible, make the flyback duty cycle as low as you can
Say have the duty cycle be 0.2 at vin=180vdc. -no more than that

- - - Updated - - -

if you observe the simulation, you can see theres too much secondary current, the duty cycle needs reducing by adjusting the turns ratio.

As you know, Always simulate before building any smps....the one above only took 10 mins.
for ccm flyback vout/vin = ND/(1-D)
where D = duty cycle
...so, at vin = 180vdc, make D = 0.2
Then calculate N=NS/NP

- - - Updated - - -

So just to summarise.............................

"""""""""""""""""""""""""""""""""Simulate first, then do it""""""""""""""""""""""""""""""""""""

That is the golden law of SMPS.

Please feel free to use the ltspice sim of post#25 and modify it to your needs.
When you've got that sim working, then, and only then, think of making it, or scoping it.
It (the sim) will only take say 10 mins or so when youre in to it.

Please feel free to use the CCM flyback excel calculation document too, also in post#25

 

[Easy peasy]

For ETD49, 212mm^2 core area, for 51T on the primary and 200uH Lpri, and 3.6A pk, 100kHz:

the core gap required is 3.64mm (centre only), or 1.8mm in each core leg (3 of) this will give you ~200uH (for 51 turns) and a lot more than 3.6A peak current capability. Flux will be only 0.07 Tesla peak, as you have more turns than you need for this core size.

You will find the performance of your converter will improve markedly under these conditions (large snubbers still required..!)

- - - Updated - - -

Your previous posts of Lp = 1.37mH imply not much gap in the core, which implies a saturating Tx core which implies very high turn off currents (>10A) - giving the big turn off spikes and ringing you have observed...!

 

[Bjtpower]

For ETD49, 212mm^2 core area, for 51T on the primary and 200uH Lpri, and 3.6A pk, 100kHz:

the core gap required is 3.64mm (centre only), or 1.8mm in each core leg (3 of) this will give you ~200uH (for 51 turns) and a lot more than 3.6A peak current capability. Flux will be only 0.07 Tesla peak, as you have more turns than you need for this core size.

You will find the performance of your converter will improve markedly under these conditions (large snubbers still required..!)

- - - Updated - - -

Your previous posts of Lp = 1.37mH imply not much gap in the core, which implies a saturating Tx core which implies very high turn off currents (>10A) - giving the big turn off spikes and ringing you have observed...!

Thank You Easypeasy
I have simulate the circuit in Psim and got to know that i can work on the 1.37 mh of inductance.
but i am not able to understand the Core saturation.

- - - Updated - - -

For ETD49, 212mm^2 core area, for 51T on the primary and 200uH Lpri, and 3.6A pk, 100kHz:

the core gap required is 3.64mm (centre only), or 1.8mm in each core leg (3 of) this will give you ~200uH (for 51 turns) and a lot more than 3.6A peak current capability. Flux will be only 0.07 Tesla peak, as you have more turns than you need for this core size.

You will find the performance of your converter will improve markedly under these conditions (large snubbers still required..!)

- - - Updated - - -

Your previous posts of Lp = 1.37mH imply not much gap in the core, which implies a saturating Tx core which implies very high turn off currents (>10A) - giving the big turn off spikes and ringing you have observed...!

What is calculation for Airgap.
i am getting very big gap that is almost 0.7cm by calculations.
Kindly verify.

How to add a spreadsheet in this..?

- - - Updated - - -

View attachment flyback calc.zip

Attached is the calculations for the discontinuous mode from Maclyman Books.

Kindly verify for the Trafo calculations

Thanks
Marx

 

[treez]

the calculation for airgap involves getting the reluctance into it and noting that reluctance = length/(u0.ur.A)

…the “length” bit is the length of the magnetic path which consists of the core bit and the gap bit…so you do that equation twice then add the two reluctances to get the overall reluctance.

Then L = N^2/reluctance.
However, there is one big problem, and that is that with etd49 size cores there is an inaccuracy due to fringing fields, so actually, the above reluctance method is of little use……I am afraid to say that the only way to do it is to already have a table of gap size vs AL values, which you make by successively grinding the gap and measuring AL value

AL = L(nH)/N^2

…..So I am afraid that unless someone is prepared to share their “gap size vs AL value” graph with you, then you have to do it by trial and error.

You could try getting some 0.1mm polyester film pieces and trying it out like that.

The problem is that you cant make the gap size too big as then the leakage gets way out of hand.
So in summary, get your 0.1mm film pieces and do it by trial and error.

- - - Updated - - -

here is all the equations that you could possible need to design a flyback transformer...youll need to pick them out but theyre all in there

 

[E-design]

I think before you go any further you must decide which mode of operation you are going to design for. Look at the attachment and once you have made that decision according to the "pros" and "cons" we can look at helping you optimizing such a design.

For the amount of power you are talking about, standard RCD snubber losses will be substantial, so it may be worth considering a non dissipating clamp design. It will add to complexity, so that is something to keep in mind also.

 

[treez]

yes single switch flyback will be a problem for rcd loss if you don't manage to really have a very low leakage inductance in the transformer.
Maybe you try a 2 transistor forward with a half bridge bootstrap driver ic?

- - - Updated - - -

posts #31 to #43 of the following....
https://www.edaboard.com/threads/349419/
...discusses use of a bootstrap half bridge driver ic for a two transistor forward converter

 

[Easy peasy]

I have simulate the circuit in Psim and got to know that i can work on the 1.37 mh of inductance.
but i am not able to understand the Core saturation.

The trouble is, its not working too well for Lpri = 1.37mH, you have no idea of the current waveshape in the mosfet - it will no doubt be peaking up due to core saturation causing the big Vspikes at turn off - change your hardware and see for your self....

its pretty clear you have no gap in your Tx at the moment, all flybacks require a gap to store energy...

Also there is a single solution to Lpri, based on thru power and Vin min (& freq), the inductance must be low enough for the current to ramp to the required level in the required time (40% of 1/freq) such that the energy per cycle delivered to the output is sufficient to meet the required power out. If the flyback voltage is too low (turns ratio) then Ton must be smaller, Lpri smaller, Ipk larger, you have about 130V of flyback, and 180Vin min so the max ON time is 13/(13+18) = 40.3% for low EMI DCM operation. When the input volts and te flyback volts are equal you can go to 50% as the rest volts on the Tx pri are opposite to the magnetising volts, silly people who try and run low flyback voltages don't understand that the OFF time will be extended as a result, the ON time must be smaller with larger Currents in the FET AND the total reverse volts on the o/p diode go up...!

 

[treez]

Yes, when I recommended simulation earlier I forgot to mention that many simulators do not simulate saturation in inductors (unless adjusted such) , so that has to be borne in mind