floorplanning...in altera....

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jay_ec_engg

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when i m writing any program in vhdl using altera max-plus II software... only sometimes altera is allowing me to do floorplaning.. i mean to say..
only some time its allowing me to change the LE location in floorplanning... but in many cases its not allowing to change any LE...
y it is so ???
 

floorplanning...in @ltera....

have u tried to use quartusii?
maybe ok
 

MaxplusII doesn't give the designer much freedom in changing the floorplan of a compiled design on the FPGA.

However, Quartus allows to do this through the LogicLock option as proper floorplanning of a relatively small design on a large FPGA chip could reduce delays.
 

what kind altera Device you used
Maybe your altera device not support Regionlock ......

but I don't understand what you maen sometimes it's working ,
and sometimes not , it 's not tool problem(QII / MaxplusII all suuport RL), I think you should check your board first.
 

floorplanning...in @ltera....

I think only quartus provides the ability of logic-lock and chip-editor. Since Altera already announced never launch a new version of maxplus, it is the time to shift the design platform from maxplus to quartus.
 

floorplanning...in @ltera....

fpga editor from Xilinx?
 

I used ACEX1k and i dont have quartus II licence.....
some times in the sense... with this chip ( i used only 27%) i m able to move LE's but if same logic i will try to load in some other FPGA .. say FLEX10K , then i m unable to move a single block..
y it is so ??
 

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