Floating point Unit in VHDL (Source Code)

[leonqin]

pls tell me details,who make it?

 

[manish12]

is it double precision or single ?


can any one check it ????????

 

[linkfox]

is it double precision or single ?


can any one check it ????????

seems to be in single, because the data inputs a, b are in 32 bits:

opa : IN std_logic_vector (31 downto 0)

 

[omara007]

is it double precision or single ?


can any one check it ????????

what is the difference between double and single precision ?

 

[FvM]

The core very much looks alike a VHDL port of Rudolf Usselmanns Open Floating Point Unit from opencores.org.

 

[omara007]

can I use a double precision unit as 2 single precision units ?

 

[dinesh.4126]

USE ieee.std_logic_misc.ALL;
why this library is used ??
ya above library is use for floating point computation .
and in the fpu_arch.vhdl input bit vector of 32 bit is their.so no floating values is their pls let me know...

 

[hamebaman]

where is the source code????

 

[Paulo A. C. Lopes]

I have made this VHDL implementation of floating point addition, subtraction, multiplication, division and square root. You can look at it or use it if you wont. Its in the atachment.

 

[ynrlakshman]

I have made this VHDL implementation of floating point addition, subtraction, multiplication, division and square root. You can look at it or use it if you wont. Its in the atachment.

Can u please send the code for Double Precision Floating Point Multiplier?

 

[samuraign]

Is it available in Verilog. Could you upload the the verilog version. Looks like singe precisions, do you have double precision FPU.
How many cycles will each function takes to complete?

 

[alex warne]

hey i am new user to this great site. i am looking for a hardware model for the floating point square root algorithm in structural design style which will cover less flip flops and less clock cycles more efficiency?

thank you

 

[shrikanthks]

I have made this VHDL implementation of floating point addition, subtraction, multiplication, division and square root. You can look at it or use it if you wont. Its in the atachment.

Sir, i couldnt find any attachments regarding this. can u please mail me the attachment. My mail id shrikanthks09@gmail.com. Thanks in advance sir.

 

[ablam]

I have made this VHDL implementation of floating point addition, subtraction, multiplication, division and square root. You can look at it or use it if you wont. Its in the atachment.

Hai,
I am new to this forum.Can u send me ur code for VHDL implementation of floating point addition, subtraction, multiplication, division and square root to ablam_k@yahoo.com.It wil be a great help.Please do the needful.I wanted it to use for my project.Thanks in advance

 

[TrickyDicky]

Altera and Xilinx both provide floating point cores for you to use.

 

[robiwan]

Just out of curiosity for an FPGA-noob, what kind of performance is to be expected for such a beast ? I'm planning on doing a synth engine, and having access to floating-point math would make things a lot easier...

 

[TrickyDicky]

What do you mean by "performance"?
You can increase the clock speed by adding pipelining, but this of course increases the latency.
Floating point cores also use a lot of resources.

 

[robiwan]

With performance I mean mainly clocks/operation (or FLOPS). I plan on using Spartan 6 with the DSP48A1 blocks, I suppose maybe those can be utilized ?

 

[TrickyDicky]

the DSP blocks are mainly geared towards fixed point. Im not sure how they get used in floating point cores, if at all. But still, a floating point operations takes several clocks to complete (from memory the standard setup for an altera FP divide is about 48 clocks latency). But the FLOPS figure is a bit meaningless. Because the blocks have a latency of 48 clocks, but you're still putting in a new value on every clock cycle. Its not like you put 1 value in an wait 48 clocks for a result. The pipelining will always alway 1 entry per clock.

 

[robiwan]

Its not like you put 1 value in an wait 48 clocks for a result... The pipelining will always alway 1 entry per clock.

But that can only be fully utilized, I assume, with the rest of the design using the FP core being pipelined ? Anyways, thanks, I think I'll stick to fixed point atm