omidsht
Member level 2
floatfixlib + vhdl+code
hello ,
I wanted to work with fixed numbers in vhdl(to be synthesible) , so in modelsim i compiled the 3 files in floatfixlib (math_utility_pkg,fixed_pkg,float_pkg) as a new lib named library ieee_proposed.
then i wrote the following code :
library ieee;
library ieee_proposed;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
entity a_ent is
port(a : in std_logic:='0';
b : out std_logic:='0';
cc : out std_logic_vector(7 downto 0)
);
end entity a_ent;
architecture a_arch of a_ent is
signal c : std_ulogic_vector(11 downto 0);
signal o :ufixed (8 downto -3);
signal int : integer range 0 to 125 :=10;
begin
process(a)
variable a1 : integer range 0 to 125 :=10;
variable a2 : integer range 0 to 255;
variable a3 : std_logic_vector(7 downto 0);
variable a4 : std_logic_vector(7 downto 0);
begin
o <= to_ufixed (a1, 8, -3);
end process;
end architecture a_arch;
but when i want to synthesize it with leonardo it gets 3 errors :
Error, ufixed is not a known type.
Error, ufixed requires 0 index values.
Error, ambigious signal assignment.
what shall i do ?
thanks in advanced , omid sharifi tehrani
hello ,
I wanted to work with fixed numbers in vhdl(to be synthesible) , so in modelsim i compiled the 3 files in floatfixlib (math_utility_pkg,fixed_pkg,float_pkg) as a new lib named library ieee_proposed.
then i wrote the following code :
library ieee;
library ieee_proposed;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;
entity a_ent is
port(a : in std_logic:='0';
b : out std_logic:='0';
cc : out std_logic_vector(7 downto 0)
);
end entity a_ent;
architecture a_arch of a_ent is
signal c : std_ulogic_vector(11 downto 0);
signal o :ufixed (8 downto -3);
signal int : integer range 0 to 125 :=10;
begin
process(a)
variable a1 : integer range 0 to 125 :=10;
variable a2 : integer range 0 to 255;
variable a3 : std_logic_vector(7 downto 0);
variable a4 : std_logic_vector(7 downto 0);
begin
o <= to_ufixed (a1, 8, -3);
end process;
end architecture a_arch;
but when i want to synthesize it with leonardo it gets 3 errors :
Error, ufixed is not a known type.
Error, ufixed requires 0 index values.
Error, ambigious signal assignment.
what shall i do ?
thanks in advanced , omid sharifi tehrani