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float question-3 errors occur in sysnthesizing with leonardo

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omidsht

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floatfixlib + vhdl+code

hello ,
I wanted to work with fixed numbers in vhdl(to be synthesible) , so in modelsim i compiled the 3 files in floatfixlib (math_utility_pkg,fixed_pkg,float_pkg) as a new lib named library ieee_proposed.
then i wrote the following code :

library ieee;
library ieee_proposed;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee_proposed.math_utility_pkg.all;
use ieee_proposed.fixed_pkg.all;


entity a_ent is
port(a : in std_logic:='0';
b : out std_logic:='0';
cc : out std_logic_vector(7 downto 0)
);
end entity a_ent;

architecture a_arch of a_ent is

signal c : std_ulogic_vector(11 downto 0);
signal o :ufixed (8 downto -3);
signal int : integer range 0 to 125 :=10;
begin


process(a)

variable a1 : integer range 0 to 125 :=10;
variable a2 : integer range 0 to 255;
variable a3 : std_logic_vector(7 downto 0);
variable a4 : std_logic_vector(7 downto 0);

begin
o <= to_ufixed (a1, 8, -3);
end process;



end architecture a_arch;


but when i want to synthesize it with leonardo it gets 3 errors :

Error, ufixed is not a known type.
Error, ufixed requires 0 index values.
Error, ambigious signal assignment.

what shall i do ?

thanks in advanced , omid sharifi tehrani
 

kvingle

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float question

what FPGA you are using?
to make it sythesizable your synthesis tool should support the package you are using . refer to documents of tool/FPGA .
 

omidsht

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Re: float question

kvingle said:
what FPGA you are using?
to make it sythesizable your synthesis tool should support the package you are using . refer to documents of tool/FPGA .
i am using Xilinx spartane , can you help me ?
 

palai_santosh

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float question

You can try with latest ISE. because xst supports the floating point lib.
 

omidsht

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Re: float question

palai_santosh said:
You can try with latest ISE. because xst supports the floating point lib.
I have ISE 10.1 , but it does not synthesize my code ?
what do you mean by float lib ?
 

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