FlipFlop area -> with & without async reset implementation

[ivlsi]

Hi All,

If to compare area of FlipFlops with and without async resets, how is an area of the FlipFlop with Async Reset bigger than area without Async Reset?

Is there a big advantage to implement FlipFlops without async reset?

Thank you!

 

[D.A.(Tony)Stewart]

The area difference of 1 AND gate is insignificant which is included in '163 counters to use clock =0 to disable propagation of CLR!=0 from an async reset.

So Sync Reset has 1 extra inverter from CLK=1 to AND gate so sync reset occurs when CLR!=0 AND CLK=0

Although return to zero or RESET on Sync CLR inputs, can occur at any time, it prevents a race during CLK transition going active high. Instead CLR is delayed until next negative transition of CLK or well after (1/2T) Sync counter has incremented.

Compare '161 with '163

 

[ivlsi]

"Compare '161 with '163" - what do you mean? what is '161? what is '163?

As for the bottom line, is an area of the flops with and without async resets approximately same?

 

[D.A.(Tony)Stewart]

Yes same. But difference assumptions on where CLR comes from.

There are over 100 CMOS variations now.
Most are compatible or at least have similar functions with the original 74161 and 74163 .

We use apostrophies (') for shortcuts. So 74LS161 becomes 'LS161 and in high voltage CMOS 74HC161 becomes 'HC161
Then 74ALVC161 becomes ....

Well if you want the similar topology of all families , I say '161

As you know none of these are the full P.N. which includes temp range and package, but each new family goes to lower Vcc or lower ESR(RdsOn) or lower power or lower latency....

 

[ivlsi]

I was recently interviewed and was told that FlipFlops without async reset take twice less area than flops with such reset... Has an interviewer misled me?
From the circuit implementation point of view, is there any advantage of the FlipFlops without async reset over the flops with such reset?
Thank you!

 

[FvM]

A standard D-FlipFlop is comprised of 4 transmission gates, two buffers and a clock inverter, requiring 18 or 20 transistors. The asynchronous reset extends the buffers to AND gates, needing just 4 additional transistors.

 

[ivlsi]

So, is there any advantage (from an implementation point of view) when a RTL designer write a FlipFlop without Async Reset instead of one with such reset?
For example, when FIFO is implemented by flops, these flops do not require reset... So, is there a matter what flops will the FIFO implemented - with or without Async Reset?