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FlipChip IO PAD design problem

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heavenevil

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Does any know about flipchip IO PAD? In our cadence design kit, I only see IO pad cell for wirebond chip, I think it's not suitable for flipchip, so anyone who has designed a flip chip PAD please give me some information, thanks. I searched google, no article related the flipchip IO cell design found, all of them talk about the routing...:???:

Just analog and VDD VSS pad are good for me, thanks. Or any documentation related to it are welcome.
 

I also wanted to know flipchip physical design. I think we dont need IO pads for flipchip design. We just have to create the bumps array and route power/ground and signals to the bumps as explains in the Encounter User Guide.

Please anyone share some knowledge regarding flipchip IO connection.
 

I also wanted to know flipchip physical design. I think we dont need IO pads for flipchip design. We just have to create the bumps array and route power/ground and signals to the bumps as explains in the Encounter User Guide.

Please anyone share some knowledge regarding flipchip IO connection.

Not exactly I think, for digital IO, you need IO cell to drive the IO, maybe only a buffer, but you need it and you can't just connect it to the bump. Besides, you need ESD protection for each IO, you can't just connect the signals to outside. Anyone have any idea about it?
 

I don't think the IO pad design for flip chips is much different than wire bond chips. The IO pad functionality is still needed like heavenevil says. The flip chip IO pads are even arranged similarly around the die compared to non-flip chip designs. A redistribution layer (RDL) is created to connect the IO pads to the flip chip bumps.
 

Ok, now we decided to design out own flip chip pad, area is the major concern, so if anyone have done that before, please please let me know and we can discuess it, thanks.
 

The best thing to do is contact the company you plan to use for assembly. They should be able to give you the design rules they need you to work to.

Keith
 

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