draser
Member level 2
Hello,
i am doing a post-synthesis vhdl netlist simulation and here is the problem i observe:
I observe that the flip flop that change from 1 to 0 change faster than the flip flops that change from 0 to 1.The first ones change i.e. at 200 ps after clock edge and the second ones at 300 ps after clock edge.
Is there any way to make these 2 transition times equal?
Thank you.
i am doing a post-synthesis vhdl netlist simulation and here is the problem i observe:
I observe that the flip flop that change from 1 to 0 change faster than the flip flops that change from 0 to 1.The first ones change i.e. at 200 ps after clock edge and the second ones at 300 ps after clock edge.
Is there any way to make these 2 transition times equal?
Thank you.