Flash memory interface to virtex2pro

[rocking_vlsi]

Hi

I need to interface external Flash memory to virtex-2P (XUP).

I am at beginner's level. plz suggest me

1) what are key issues that i should know before starting.

2) which are popular flash memory communication protocols.


Thanks in advance....

 

[cks3976]

Which flash ? and what is the purpose of this flash ? Is it a NAND flash or a serial flash ? Please let us know the memory size and whether you need a serial or parallel flash. Based on that you will need to implement the memory controller in your FPGA. Also check FPGA datasheet for availability of hardened memory controller such as I2C, or SPI if you are planning to use serial memory device.

 

[rocking_vlsi]

Thanks...

It is serial NAND Flash of size 1Gb....

I have XUP Virtex II Pro to start with. Give me suggestions to start designing Memory controller on FPGA.
Where to get knowledge on timing constraints when designing on FPGA

 

[cks3976]

Serial flash.. OK, which protocol ? SPI ? or I2C ? in either cases you will get memory controllers on open source that can be directly implemented in CPLD/ FPGA.

If this is an I2C memory..
**broken link removed**
http://www.xilinx.com/support/documentation/application_notes/xapp385.pdf
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If this is SPI memory..
http://www.altera.com/literature/an/an485.pdf
https://www.edaboard.com/threads/45479/


Regarding specifying timing constraints in FPGA (some of them are specially for Xilinx flow), following links might be of some use:
RTL coding guidelines, static timing analysics for fpga asic
**broken link removed**
https://www.edaboard.com/threads/12309/
Xilinx timing constraints | FPGA Central
FPGA design tutorial: FPGA implementation (Xilinx flow)
http://www.cse.psu.edu/~eachempa/CSE478/timespec_15.pdf
www.markharvey.info
http://digsys.upc.es/sed/ED/unitats/unitat_2_3/lattice_dec1306_clock_problems_digital_systems.pdf
Why should I care about latches?

 

[rocking_vlsi]

Thanks CKS...

links you provided are very nice.. i will go through them....

For my knowledge purpose I want to know

1) what is criteria to select flash serial/parallel
2) how flash memory differs for various application.

 

[cks3976]

1) what is criteria to select flash serial/parallel
2) how flash memory differs for various application.

Serial / Parallel flash selection depends on what is the type of memory controller you are using, memory density, speed of Read/Write and purpose of the memory. For example to store a Reset configuration, or a BIOS, a serial Flash/EPROM would be a better choice because they need a smaller footprint (memory and PCB), low cost and easily replaceable in the field. Where as if you want to store a bigger chunk of data, say for example, a secondary stage boot loader, or an application software, parallel Flash could be (not always) a better choice.

Check this link, this differentiate between NOR and NAND memories. Choice between NOR and NAND flash is based on parameters such as cost per bit of storage, speed of writing, speed of accessing the data etc.,

http://umcs.maine.edu/~cmeadow/cour..._vs_NOR_Flash_Memory_Technology_Overviewt.pdf
https://www.edaboard.com/threads/97307/