Fixing MaxCap violations in Cadence SOC Encounter Tool

[biju4u90]

While doing PnR, its shown that my design is having a MaxCap violation in the clock pin.

# Net / InstPin MaxCap Cap CapSlack CellPort Remark
#
clk
clk 0.012 0.026 -0.014 C

*info: there is 1 max_cap violation in the design.
*info: 0 violation is real.
*info: 1 violation may not be fixable:
*info: 1 violation on clock net (remark C).

Optimization is not solving the issue. How can I fix MaxCap violations?
Can anybody please help? Thanx in advance.

 

[artmalik]

You will have to fix by using the constraing
setMaxCapPerFreq to the values you desire and Optdesign will treat it as a design constraint and fix it globally. Max_tran, Max_Cap are DRV's which are fixed during optimization.

 

[rca]

As you mentionned, the violation is on a clock net, so any max cap optimisation step will not changed any thing on the clock network.
The CTS step must fix that if not you could increase the cell drive of the cell by yourself.

 

[biju4u90]

As you mentionned, the violation is on a clock net, so any max cap optimisation step will not changed any thing on the clock network.

Does this mean that the optimisation using the set_max_transition and set_max_capacitance won't work here because the violation is on the clock net?? Is it possible that the issue could be solved using these constraints if the violation was on some other nets other than the clock net?

 

[rca]

Right as the issue is on the clock net, you could not fix them with opt steps.
You need to fix that at the CTS step.