biju4u90
Full Member level 3
While doing PnR, its shown that my design is having a MaxCap violation in the clock pin.
# Net / InstPin MaxCap Cap CapSlack CellPort Remark
#
clk
clk 0.012 0.026 -0.014 C
*info: there is 1 max_cap violation in the design.
*info: 0 violation is real.
*info: 1 violation may not be fixable:
*info: 1 violation on clock net (remark C).
Optimization is not solving the issue. How can I fix MaxCap violations?
Can anybody please help? Thanx in advance.
# Net / InstPin MaxCap Cap CapSlack CellPort Remark
#
clk
clk 0.012 0.026 -0.014 C
*info: there is 1 max_cap violation in the design.
*info: 0 violation is real.
*info: 1 violation may not be fixable:
*info: 1 violation on clock net (remark C).
Optimization is not solving the issue. How can I fix MaxCap violations?
Can anybody please help? Thanx in advance.